diff --git a/main.py b/main.py
index d88e376c53af17be325864d618d94ae06780700d..fd2fddd0e6d4b1b5b2dfba423dc9d45ac5edb4ea 100644
--- a/main.py
+++ b/main.py
@@ -47,14 +47,14 @@ class CacheSimulator():
"""
Program main.
"""
- print('\n')
- print('main():')
- print(' s: {0}'.format(s))
- print(' E: {0}'.format(E))
- print(' b: {0}'.format(b))
- print(' file_name: {0}'.format(file_name))
- print(' verbose: {0}'.format(verbose))
- print('')
+ # print('\n')
+ # print('main():')
+ # print(' s: {0}'.format(s))
+ # print(' E: {0}'.format(E))
+ # print(' b: {0}'.format(b))
+ # print(' file_name: {0}'.format(file_name))
+ # print(' verbose: {0}'.format(verbose))
+ # print('')
if verbose:
self.verbose = True
@@ -68,7 +68,8 @@ class CacheSimulator():
self.B = int(math.pow(2, self.b))
self.m = self.E * self.S
# self.M = int(math.pow(2, self.m))
- self.M = int(math.pow(2, 64))
+ self.M = int(math.pow(2, 8))
+ # self.M = int(math.pow(2, 64))
# self.debug_print()
@@ -87,9 +88,9 @@ class CacheSimulator():
'block': [],
})
- # Display initial cache.
- self.print_cache()
- print('\n\n')
+ # # Display initial cache.
+ # self.print_cache()
+ # print('\n\n')
# Run simulation on cache, using file.
self.run_simulation(file_name)
@@ -163,29 +164,44 @@ class CacheSimulator():
# Use masks to get address chunks.
parsed_data['block'] = address & block_mask
- set = (address & set_mask) >> block_offset
- parsed_data['set'] = set
- tag = (address & tag_mask) >> (block_offset + set_offset)
- parsed_data['tag'] = tag
+ parsed_data['set'] = (address & set_mask) >> block_offset
+ parsed_data['tag'] = (address & tag_mask) >> (block_offset + set_offset)
# print('address: {0} As Bits: {0:b}'.format(address))
# print('block: {0} As Bits: {0:b}'.format(parsed_data['block']))
# print('set: {0} As Bits: {0:b}'.format(parsed_data['set']))
# print('tag: {0} As Bits: {0:b}'.format(parsed_data['tag']))
- # We have our values. Now compare against the all entries in the cache.
- for index in range(len(self.cache[set])):
- # Check if match.
- if self.cache[set][index]['valid'] is True and self.cache[set][index]['tag'] == tag:
- # Match found.
- return self.process_hit(line, parsed_data, index, main_bool)
- else:
- # Not a match. Examine why.
- if self.cache[set][index]['valid'] is False:
- # Cache location was not set. Cold miss. We can just set and return.
- return self.process_miss(line, parsed_data, index, main_bool)
-
- # If we made it this far, cache locations were set, but tags did not match. Conflict miss.
- return self.process_eviction(line, parsed_data, main_bool)
+ # Check which of 3 operations apply.
+ if split_line[1] == 'L':
+ # Is load.
+ self.process_load(line, parsed_data, main_bool)
+
+ elif split_line[1] == 'S':
+ # Is store.
+ self.process_store(line, parsed_data, main_bool)
+
+ elif split_line[1] == 'M':
+ # Load then store.
+ load_result = self.process_load(line, parsed_data, False)
+ store_result = self.process_store(line, parsed_data, False)
+
+ # Check if this is an instruction directly from file.
+ if main_bool and self.verbose:
+ # Is instruction from file. Print data.
+ if load_result == 0 and store_result == 0:
+ print('{0} hit hit'.format(line))
+ elif load_result == 1 and store_result == 0:
+ print('{0} miss hit'.format(line))
+ elif load_result == 2 and store_result == 0:
+ print('{0} miss eviction hit'.format(line))
+ elif load_result == 1 and store_result == 1:
+ print('{0} miss miss'.format(line))
+ else:
+ print('{0} miss eviction miss'.format(line))
+
+ else:
+ # Unknown operation.
+ raise ValueError('Unknown operation "{0}"'.format(split_line[1]))
def print_cache(self):
"""
@@ -198,6 +214,63 @@ class CacheSimulator():
print(' Line {0}: {1}'.format(line_index, self.cache[set_index][line_index]))
print('')
+ def process_load(self, line, parsed_data, main_bool):
+ """
+ Handle load instruction. Always misses?
+ :param line: Original line read in.
+ :param parsed_data: Data parsed from line.
+ :param main_bool: Bool to indicate if this is an initial cache line read in or a subquery from one.
+ Note that only initial cache line read ins will print or update missed/skipped/evicted variables.
+ :return: 1 for unconditional miss?
+ """
+ set = parsed_data['set']
+
+ # Compare against the all entries in the cache for match.
+ for index in range(len(self.cache[set])):
+ # Check if match.
+ if self.cache[set][index]['valid'] is True and self.cache[set][index]['tag'] == parsed_data['tag']:
+ # Match found.
+ self.process_miss(line, parsed_data, index, main_bool)
+ return 1
+
+ # If we got this far, then no match was found. Get least recently used index.
+ try:
+ index = self.access_log[set][0]
+ except IndexError:
+ # Set has not been accessed yet. Use first index.
+ index = 0
+ self.process_miss(line, parsed_data, index, main_bool)
+ return 1
+
+ def process_store(self, line, parsed_data, main_bool):
+ """
+ Handle store instruction. Works as described in class video.
+ :param line: Original line read in.
+ :param parsed_data: Data parsed from line.
+ :param main_bool: Bool to indicate if this is an initial cache line read in or a subquery from one.
+ Note that only initial cache line read ins will print or update missed/skipped/evicted variables.
+ :return: 0 on hit | 1 on miss | 2 on eviction.
+ """
+ set = parsed_data['set']
+
+ # Compare against the all entries in the cache for match.
+ for index in range(len(self.cache[set])):
+ # Check if match.
+ if self.cache[set][index]['valid'] is True and self.cache[set][index]['tag'] == parsed_data['tag']:
+ # Match found.
+ self.process_hit(line, parsed_data, index, main_bool)
+ return 0
+ else:
+ # Not a match. Examine why.
+ if self.cache[set][index]['valid'] is False:
+ # Cache location was not set. Cold miss. We can just set and return.
+ self.process_miss(line, parsed_data, index, main_bool)
+ return 1
+
+ # If we made it this far, cache locations were set, but tags did not match. Conflict miss.
+ self.process_eviction(line, parsed_data, main_bool)
+ return 2
+
def process_hit(self, line, parsed_data, index, main_bool):
"""
Processes simulated cache for a hit.
diff --git a/wmucachelab/traces/class_video_example.trace b/wmucachelab/traces/class_video_example.trace
index abd60228aa8be862b1bef1d54b0a8bacf57356d9..bc0c62d3bef5c3f6ff9a613341f928c1ef4dccb9 100644
--- a/wmucachelab/traces/class_video_example.trace
+++ b/wmucachelab/traces/class_video_example.trace
@@ -1,5 +1,5 @@
- L 0,1
- L 1,1
- L 7,1
- L 8,1
- L 0,1
+ S 0,1
+ S 1,1
+ S 7,1
+ S 8,1
+ S 0,1